1. Field of the Invention
The present invention relates to internal power supply voltage generation circuits, internal voltage generation circuits, and semiconductor devices, and more particularly, to an internal power supply voltage generation circuit immune to variation in external power supply voltage and temperature, an internal voltage generation circuit immune to variation in power supply voltage, and a semiconductor device immune to variation in internal power supply voltage.
2. Description of the Background Art
FIG. 13 is a circuit diagram showing in detail an internal voltage-down power supply circuit as a conventional internal power supply voltage generation circuit.
Referring to FIG. 13, an internal voltage-down power supply circuit 94 generates and supplies to a control circuit group 63 an internal power supply voltage intVcc. Control circuit group 63 includes a plurality of control circuits which operate according to internal power supply voltage intVcc. Internal voltage-down power supply circuit 94 includes a comparator circuit 67 and a voltage-down circuit 1. Voltage-down circuit 1 is formed of a PMOS transistor. Comparator circuit 67 is formed of a current mirror type amplify circuit. Comparator circuit 67 includes PMOS transistors 7 and 9, NMOS transistors 11 and 13, and a constant current source 69.
An output voltage from comparator circuit 67 is applied to the gate of PMOS transistor 1. PMOS transistor 1 down-converts an external power supply voltage extVcc according to the level of the output voltage to generate internal power supply voltage intVcc. A reference voltage Vref is applied to the gate of NMOS transistor 13 of comparator circuit 67. Internal power supply voltage intVcc generated from PMOS transistor 1 is applied to the gate of NMOS transistor 11 of comparator circuit 67. Therefore, comparator circuit 67 provides a voltage to the gate of MOS transistor 1 so that the level of internal power supply voltage intVcc is equal to the level of reference voltage Vref.
FIG. 14 is a schematic block diagram of a conventional semiconductor device. Components corresponding to those of FIG. 13 have the same reference characters allotted, and their description will not be repeated.
Referring to FIG. 14, a conventional semiconductor device includes four memory arrays 97, and external power supply pad 95, an internal voltage-down power supply circuit 94, a power line 71, and a control circuit group 63. Memory array 97 includes a plurality of memory cells to store data. Internal voltage-down power supply circuit 94 is located in the proximity of external power supply pad 95 provided at the end of the chip. External power supply pad 95 serves to supply external power supply voltage extVcc to internal voltage-down power supply circuit 94. Power line 71 serves to supply internal power supply voltage intVcc generated from internal voltage-down power supply circuit 94 to control circuit group 63.
As described above, a conventional internal voltage-down power supply circuit forms a closed loop in which the output which is internal power supply voltage intVcc is applied to comparator circuit 67. When external power supply voltage extVcc is shifted to a greater value, or when the temperature during the operation of internal voltage-down power supply circuit 94 is low, the channel conductance of the transistors forming internal voltage-down power supply circuit 94 becomes greater to increase the voltage gain of comparator circuit 67 and voltage-down power supply circuit 1. This induces the problem that internal power supply voltage intVcc is easily oscillated unnecessarily which is the output of internal voltage-down power supply circuit 94.
As described above, a conventional semiconductor device has internal voltage-down power supply circuit 94 provided at the end of the chip. If control circuit group 63 that operates according to internal power supply voltage intVcc is arranged remote from internal voltage-down power supply circuit 94, the resistance of power line 71 is increased. This causes the level of internal power supply voltage intVcc in the proximity of control circuit group 63 to become lower than the level of internal power supply voltage intVcc in the proximity of internal voltage-down power supply circuit 94 by the parasitic resistance of power line 71 when the power consumption of control circuit group 63 is increased. It is to be noted that internal voltage-down power supply circuit 94 generates internal power supply voltage intVcc by feeding back internal power supply voltage intVcc in the proximity of internal voltage-down power supply circuit 94. There was a problem that internal voltage-down power supply circuit 94 does not easily follow the variation of internal power supply voltage intVcc in the proximity of control circuit group 93.